In the production of CMOS integrated circuity, process variables can significantly affect the performance characteristics of many of the devices, particularly driver devices formed on the chip. These performance characteristics include delay, rise and fall time, and impedance etc. The process variables which affect these performance characteristics include variation of channel length, thickness of the dielectric in the gate electrode channel and diffusion channel width, and supply voltage etc. All of these factors can have a significant cumulative effect on the circuit operation. As is well known, when the driver circuit is designed to drive a certain load, if the driver circuit operates too fast, noise will be generated and interfere with signal recognition. On the other hand, if the circuit operates too slow, performance time is impaired. Since cost effective arrangements for eliminating these process variations are not readily available in the present state of the art, it has become necessary to provide compensation in the circuit for such variables.
Suitable compensation is provided by the circuit described in U.S. Pat. No. 4,975,599, issued on Dec. 4, 1990, wherein a CMOS circuit includes a compensating device having a performance characteristic which varies in a similar manner as that of a driver device and which is arranged in the circuit such that its output acts in compensating opposition to the output of the driver device. This arrangement suitably resolves the above noted variations in performance, however, it necessitates a given level of circuit complexity, and requires additional power which can be of critical importance in low power applications.